Senior ASIC RTL Design Engineer, AI Hardware

Description: Join Cerebras Systems as a Senior ASIC RTL Design Engineer to design and develop the next generations of the Cerebras Wafer Scale Engine (WSE). Collaborate with cross-functional teams to deliver high-performance, power-efficient, and scalable semiconductor architectures. Requirements: Master’s degree in Computer Science, Electrical Engineering, or equivalent. 8+ years of experience in complex, high-performance RTL designs. Expertise in Front End Chip integration and third-party IP integration. Experience in high-performance computing, GPU/CPU designs, or machine learning. Knowledge of networking stacks (TCP/IP, RDMA, Ethernet), PCIe, CPU interfaces, and Serdes technology. Proficient in scripting tools such as Python and TCL. Benefits: Competitive salary range of $200,000 to $290,000 annually, with potential bonuses and equity. Opportunity to work on groundbreaking AI technology in a non-corporate, inclusive work culture.